University of California, Santa Barbara
Department of Electrical and Computer Engineering

Synthesis and CAD
ECE 156B, Winter 2014
Instructor: Prof. Li-C. Wang
licwang@ece.ucsb.edu
(805)893-5916 
Schedule: Class: TTh 5-6:15 pm at PHELPS 2516
Office: Room 3161, Engineering I
Office Hour: After class or by appointment

Syllabus  (see first lecture below)

TAs Office Hours and Discussion/Lab Session

Kuo-Kai Hsieh, kuokai@umail.ucsb.edu  Officer Hours: Monday 3:00 - 4:30pm & Thursday 10:00 - 11:30am

TAs are usually working in my research lab at HRH 2164. Find them there.
Lab session is converted into TA discussion and Q/A session

 

Online Class Orgazination

Date

Lecture

Topic

Homework

Solutions

Notes

Jan. 7

Syllabus

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Jan. 9 Introduction Why validation is important      
Jan. 14, 16 Multi-level logic optimization Factoring      
Jan. 21, 23, 28, 30
Feb. 4		 SAT Boolean Satisfibility in EDA This is a tutorial presented at CAV 2000. You may also want to read the milestone SAT paper GRASP.
zChaff pacakge 		   

Feb 6, Mid-term Exam (In class)
Feb 4, Feb 11 OBDD (Chapter 6 of orange book) OBDD CUDD package
Original BDD paper 		   
Feb 18, 20 Equivalence Checking
Simbolic Simulation		 BEQ & Symbolic Simulation Motorola symbolic simulation paper    
Feb 20 Fault Modeling Fault Modeling    
Feb 25, 27 Functional Verification Functional Verification

The original RTPG paper in IBM Journal of R&D
IBM team defined the methodology of RTPG, the current practical tool for functional verification.

The IBM's paper in DAC 95 (follow up)
Built upon their earlier success, this work improved and applied RTPG to PowerPC microprocessor platform.

The Alpha Team's paper in DAC 98
For the first time, a company reports the results of applying RTPG in functional verification in detail.

Motoroal's RTPG methodology is reported in this MTV2001 paper. This team were used to be my colleagues at IBM-Motorola-Apple PowerPC design center alliance. In a way, we got the RTPG methodology from IBM during this alliance.

Modern commercial functional verification tool utilizes constraint solver as the underlying engine. This paper is an excellent source to describe the constraint solving problem and provide a solution from Synposys perspective.
 

    
Mar 4 DSM Timing Issues Timing issues in DSM domain      

 

Projects And Homework

You will be using Design Compiler (DC), the synposys synthesis tool. For DC, you can only use it in the ECI lab. Hence, please get an account in the ECI lab if you don't have one now. Also, you are expected to know ModelSim (also available in the ECI lab) or a similar Verilog simulator from ECE 156A.

Electrical and Computer Engineering || College of Engineering