Publications From 2001-2003 (With UCSB Affliation):

1. "Predicting Defect Level and Defect Detection Behavior: Logic Models Vs. Statistical Timing Defects" Li-C. Wang, Angela Krstic, Kwang-Ting Cheng, Ray Mercer, Thomas Williams, Magdy Abadir, to appear in International Test Conference, Oct, 2003
2. "Diagnosis-Based Post-Silicon Timing Validation Using Statistical Tools and Methodologies" Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, T.M. Mak, to appear in International Test Conference, Oct, 2003
3. "Enhancing Diagnosis Resolution for Delay Defects Based Upon Statistical Timing Models" Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, Jing-Jia Liou, T. M. Mak, to appearl in ACM/IEEE Design Automation Conference, June, 2003
4. "A Signal Correlation Guided ATPG Solver and Its Applications For Solving Difficult Industrial Cases" Feng Lu, Li-C. Wang, Kwang-Ting Cheng, John Moondanos, Hanna Ziyad, to appearl in ACM/IEEE Design Automation Conference, June, 2003
5. Diagnosis of Delay Defects Using Statistical Timing Models" Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, Jing-Jia Liou, in Proc. IEEE VLSI Test Symposium, April 2003
6. "Delay Defect Diagnosis Based Upon Statistical Timing Models -- The First Step" Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, Jing-Jia Liou, in Proc. DATE 2003
7. "A Cirucit SAT Solver with Signal Correlation Guided Learning" Feng Lu, Li-C. Wang, Kwang-Ting Cheng, Ric C-Y. Huang, in Proc. DATE, 2003
8. "On Structural Vs. Functional Testing for Delay Faults" Angela Krstic, Jing-Jia Liou, Kwang-Ting Cheng, Li-C. Wang, in Proc. ISQED, 2003
9. "Experience in Critical Path Selection For Deep Sub-Micron Delay Test and Timing Validation" Jing-Jia Liou, Li-C. Wang, Angela Krstic, Kwang-Ting Cheng, in Proc. ACM/IEEE ASP Design Automation Conference, 2003
10. "Enhanced Symbolic Simulation For Efficient Verification of Embedded Array Systems" Tao Feng, Li-C. Wang, Kwang-Ting Cheng, Manish Pandey, and Magdy S. Abadir, in Proc. ACM/IEEE ASP Design Automation Conference, 2003
11. "Delta-Sigma Modulator Based Mixed-signal BIST Architecture for SoC," Chee-Kian Ong, Kwang-Ting (Tim) Cheng and Li.-C Wang, in Proc. ACM/IEEE ASP Design Automation Conference, 2003
12. "Theoretical and Practical Considerations of Path Selection for Delay Fault Testing" Jing-Jia Liou, Li-C. Wang, and Kwang-Ting Cheng, in Proc. International Conference on Computer-Aided Design (ICCAD), San Jose, Nov, 2002
13. "Fortuitous Detection and its Impact on Test Set Sizes Using Stuck-at and Transition Faults," J. Dworak, J. Wingfield, B. Cobb, S. Lee, L-C. Wang, and R. Mercer, in Proc. IEEE Defect and Fault-Tolerance Symposium, Vancouver BC, Nov 2002
14. "Testing High-Performance Custom Circuits without Explicit Testing of The Internal Faults" Li-C. Wang, Magdy S. Abadir, and Juhong Zhu, in Proc. International Test Conference, Baltimore, Oct 2002
15. "Analysis of Delay Test Effectiveness with Multiple-Clocked Scheme" Jing-Jia Liou, Li-C. Wang, and Kwang-Ting Cheng, J. Dworak, R. Mercer, R. Kapur, T. W. Williams, in Proc. International Test Conference, Baltimore, Oct 2002
16. "Combining ATPG and Symbolic Simulation for Efficient Validation of Array Systems,” G. Parthasarathy, M. K. Iyer, T. Feng, Li-C. Wang, Kwang-Ting Cheng, and Magdy S. Abadir, in Proc. International Test Conference, Baltimore, Oct 2002
17. "False-Path-Aware Statistical Timing Analysis and Efficient Path Selection for Delay Testing and Timing Verification"  Jing-Jia Liou, Angela Krstic, Li-C. Wang, and Kwang-Ting Cheng, in Proc. ACM/IEEE Design Automation Conference, New Orlean, June 2002
18. "Enhancing Test Efficiency for Delay Fault Testing Using Multiple-Clocked Schemes" JingJia Liou, Li-C. Wang, Kwang-Ting Cheng, J. Dworak, R. Mercer, R. Kapur, T. W. Williams, in Proc. ACM/IEEE Design Automation Conference, 2002
19. "Module Placement with Boundary Constraints Using the Sequenc-Pair Representation" J. Lai, M-S. Lin, T-C. Wang, and Li-C. Wang, in ACM/IEEE ASP Design Automation Conference, 2001, pp. 515-520.
20. "Defect-Oriented Testing and Defective Part Level Prediction for Commercial Sub-Micron ICs" J. Dworak, J. Wicker, S. Lee, M. Grimaila, M. R. Mercer, K. Butler, B. Stewart, and Li-C. Wang, IEEE Design and Test of Computers, January/February 2001, Vol. 18, No. 1, pp 31-41.
21. "Analysis of  Testing Methodologies for Custom Designs in PowerPC Microprocessor" Magdy S. Abadir, Juhong Zhu, and Li-C. Wang, , in Proc. IEEE VLSI Test Symposium, Los Angeles, CA, April 2001, pp 252-257

1. "On Efficiently Producing Quality Tests for Custom Circuits in PowerPC Microprocessors," Li-C. Wang and Magdy S. Abadir, coming issue, Journal of Electronic Testing
2. "Experiences in Validation of PowerPC Mircoprocessor Embedded Arrays," Li-C. Wang and Magdy S. Abadir, coming issue, Journal of Electronic Testing
3. "Test Generation Based on High Level Assertion Specification for PowerPC^TM Microprocessor Arrays," Li-C. Wang and Magdy S. Abadir, Journal of Electronic Testing, No. 13, 1998
4. "On Measuring the Effectiveness of Various Design Validation Approaches for PowerPC^TM Microprocessor Arrays," Li-C. Wang, Magdy S. Abadir, and Jeng Zeng, ACM Transactions on Design Automation (TODAES), Jan 1999
5. "Enhanced DO-RE-ME Based Defect Level Prediction Using Defect Site Aggregation MPGD" J. Dworak, M.R. Grimaila, S. Lee, Li-C. Wang, and M.R. Mercer, in Proceedings of the 2000 International Test Conference, Atlantic City, NJ; September 2000, pp 930-939
6. "On the Superiority of DO-RE-ME/MPG-D Over Stuck-at Based Defective Part Level Prediction," J. Dworak, M.R. Grimaila, B. Cobb, T-C. Wang, Li-C. Wang, and M.R. Mercer, in Proceedings of IEEE Asian Test Symposium, Taipei, Taiwan, Dec 2000, pp 151-157
7. "Tradeoff Analysis for Generating High Quality Tests for Custom Circuits in PowerPC Microprocessor," Li-C. Wang and Magdy S. Abadir, International Test Conference, Atlantic City, NJ, 1999
8. M.R. Grimaila, S. Lee, J. Dworak, K.M. Butler, B. Stewart, H. Balachandran, B. Houchins, V. Mathur, J. Park, Li-C. Wang, and M.R. Mercer, "REDO - Probabilistic Excitation and Deterministic Observation - First Commercial Experiment," Proceedings of the 1999 VLSI Test Symposium (VTS99); Dana Point, CA; April 1999, pp. 268-274
9. "Automatic Generation of Assertions for Formal Verification of PowerPC^TM Microprocessor Arrays Using Symbolic Trajectory Evaluation," Li-C. Wang, Magdy S. Abadir, and Nari Krishumuthy, in Proc. 34^th Design Automation Conference, San Francisco, June 1998
10. "On Logic and Transistor Level Design Error Detection of Various Validation Methods for PowerPC^TM Microprocessor Arrays," Li-C. Wang, Magdy S. Abadir, Jeng Zeng, in Proc. IEEE VLSI Test Symposium, Monterey, April, 1998
11. "Measuring the Effectiveness of Various Design Validation Approaches for PowerPC^TM Microprocessor Arrays," Li-C. Wang, Magdy S. Abadir, and Jeng Zeng, in Proc. Design, Automation and Test in Europe (DATE), Paris, France, Feb 1998 (Best Paper Award)
12. "Practical Considerations in Formal Equivalence Checking of PowerPC^TM Microprocessors," Arun Chandran, Li-C. Wang, and Magdy S. Abadir, in Proc. Eighth Great Lakes Symposium on VLSI, Lafayette, Louisiana, Feb 1998.
13. "A New Validation Methodology Combining Test and Formal Verification for PowerPC^TM Microprocessor Arrays," Li-C. Wang, and Magdy S. Abadir, Proc. 28th International Test Conference, Washington DC, 1997, pp. 954-963
14. "Using Target Faults to Detect Non-Target Defects," Li-C. Wang, M. Ray Mercer, and Thomas W. Williams, Proc. 27th International Test Conference, Washington DC, 1996, pp. 629-638
15. "A Better ATPG Algorithm and Its Design Principles," Li-C. Wang, M. Ray Mercer, and Thomas W. Williams, Proc. International Conference on Computer Design, Austin, Texas 1996, pp. 248-253
16. "On Efficiently and Reliably Achieving Low Defective Part Levels," Li-C. Wang, M. Ray Mercer, and Thomas W. Williams, Proc. 26th International Test Conference, Washington DC, 1995, pp. 616-625
17. "On the Decline of Test Effectiveness as Fault Coverage Approaches 100%," Li-C. Wang, M. Ray Mercer, and Thomas W. Williams, Proc. 13th IEEE VLSI Test Symposium, Princeton, NJ. 1995, pp. 74-83
18. "Enhanced Test Performance Via Unbiased Test Sets," Li-C. Wang, M. Ray Mercer, and Thomas W. Williams, Proc. European Design and Test Conference, Paris, France, 1995, pp. 294-302
19. "Experience in Massively Parallel Discrete Event Simulation," Albert G. Greenberg, Boris D. Lubachevsky, and Li-C. Wang, Proc. ACM Symposium on Parallel Algorithms and Architectures, Velen, Germany, 1993.
20. "Parallel Algorithms and Complexity Results for Telephone Link Simulation," V. Ramachandran and Li-C. Wang, Proc. IEEE Symposium on Parallel and Distributed Processing, Dallas, Texas, 1991, pp. 378-385
21. "Experience in Validation of PowerPC Microprocessors," Li-C. Wang and Magdy S. Abadir, in Digest of Paper of IEEE International Workshop on Microprocessor Test and Verification, Washington DC, 1998
22. "On Design Error Detection of Different Validation Approaches for PowerPC^TM Microprocessor Arrays," Li-C. Wang, Magdy S. Abadir, Jeng Zeng, in Digest of Paper of IEEE International High Level Design Validation and Test, Workshop, Oakland, CA, Nov 1997, pp. 45-52
23. "New Criteria for ATPG Design and Their Implications," Li-C. Wang, M. Ray Mercer, and Thomas W. Williams, Proc. IEEE European Test Workshop, Sete, France, 1996.
24. "Enhancing Test Performance by Reducing Biases," M. Ray Mercer, Li-C. Wang and Thomas W. Williams, IEEE Design for Testability Workshop, Boulder, CO 1996.
25. "The Telephone Connection Problem," V. Ramachandran and Li-C. Wang,Technical Report TR-91-16, Computer Science Dept, UT-Austin, 1991

• ECE 156A, Fall 05
• ECE 156B, Winter 04
• ECE 255B, Spring 04

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