10th International Workshop on

 Microprocessor Test and Verification
(MTV'09)
Common Challenges and Solutions
December 7-8, 2009, Austin, Texas, USA
Cooperating entities: IEEE
Freescale Semiconductor
IBM
Austin DVClub
General Chair: Magdy S. Abadir (M.Abadir@freescale.com), Freescale
Program Co-Chair: Jay Bhadra (Jayanta.Bhadra@freescale.com), Freescale
Program Co-Chair: Li-C. Wang (licwang@ece.ucsb.edu), UCSB
Call for Papers

MTV 2009 Call for Papers (PDF)

Paper Submission
Papers: Authors are invited to submit postscript or PDF versions of their papers (maximum 6 pages), with author names, affiliation, addresses, telephone and fax numbers, e-mail address, and the person who will present the work if accepted. Authors of accepted papers can choose to submit the full paper for inclusion in the formal Workshop proceeding published by IEEE.

AUTHOR’S SCHEDULE: Submission deadline: Sept 1, 2009; Notification: Oct 1, 2009; Final version: Nov 1, 2009

Special Sessions, Panels and Tutorials: Proposals for special sessions, panels and tutorials are also invited. Please email the abstract of your proposals directly to the program chair as early as possible before paper submission deadline.

Submission website: Coming soon

Final program and presentations
Coming soon

Hotel  
Coming soon

Conference Registration
Coming soon

Description - Workshop Scope

The purpose of MTV'09 is to bring together researchers and practitioners from all areas of work related to verification and test in order to exchange innovative ideas and present new methodologies for solving the challenges facing us today in various processor and SOC design environments. The workshop will take place in Austin, Texas, the live music capital of the world.

Areas of Interest
  • Validation of microprocessors and SOCs
  • Experiences on test and verification of high performance processors and SOCs
  • Test/verification of multimedia processors and SOCs
  • Performance testing
  • High-level test generation for functional verification
  • Emulation techniques
  • Silicon debugging
  • Formal techniques and their applications
  • Verification coverage
  • Test generation at the transistor level
  • Equivalence checking of custom circuits at the transistor level
  • ESL Methodology
  • Virtual Platforms
  • Software verification
  • Circuit level verification
  • Switch-level circuit modeling
  • Timing verification techniques
  • Path analysis for verification or test
  • Design error models
  • Design error diagnosis
  • Design for testability or verifiability
  • Optimizing SAT procedures for application to testing and formal verification
Organizing Committee
Finance: Aseem Gupta (UC-Irvine)
Publication: Himyanshu Anand (Freescale)
Panel: Al Crouch (Inovys)
Publicity: Eric Hennenhofer (Obsidian)
Committee:
 Andreas Veneris (U. of Toronto)
European/Canadian Moshe Levinger (IBM)
Program Committee
Jacob Abraham (UT-Austin)
Miron Abramovici (DAFCA)
Hussain Al-Asaad (UC-Davis)
Tony Ambler (UT-Austin)
Eyal Bin (IBM)
Shawn Blanton (CMU)
Melvin Breuer (USC)
Ken Butler (TI)
K.-T. (Tim) Cheng (UCSB)
Nick Dutt (UCI)
Sujit Dey (UCSD)
Ajit Dingankar (Intel)
Harry Foster (Mentor)
Franco Fummi (Universita `di Verona)
Michael Garcia (Freescale)
Sandeep Gupta (USC)
Ian Harris (UC-Irvine)
John Hayes (U. Michigan)
Eric Hennenhofer (Obsidian)
Jim Holt (Freescale)
Alan J.Hu (U. British Columbia)
T. M. Mak (Intel)
Anmol Mathur (Calypto)
Hillel Miller (Freescale)
Sankaran Menon (Intel)
Ishwar Parukar (Sun)
Carl Pixley (Synopsys)
Paolo Prinetto (Poli di Torino)
Sandip Ray (UT-Austin)
Xiao Sun (Intel)
Alex Tetelbaum (LSI)
Nur Touba (UT-Austin)
Miroslav Velev (Aries)
Vivekananda Vedula (Intel)
Hung-Pin Charles Wen (National Chiao-Tung U.)
Cheng-Wen Wu (National Tsing-Hua U.)
Paul R Zehr (Intel)
Jing Zeng (AMD)
Yervant Zorian (VirageLogic)
Past MTV workshop Information

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Last modified: 06/19/2009
URL: http://mtv.ece.ucsb.edu/MTV/