Microprocessor Test Verification

8th International Workshop on

Microprocessor Test and Verification
(MTV'07)
Common Challenges and Solutions
December 5-6, 2007, Austin, Texas, USA

Sponsored by:	IEEE Computer Society Test Technology Technical Council

General Chair:	Magdy S. Abadir (M.Abadir@freescale.com), Freescale
Program Chair:	Li-C. Wang (licwang@ece.ucsb.edu), UCSB
Program Co-Chair:	Jay Bhadra (Jayanta.Bhadra@freescale.com), Freescale

2007 Advance Program

The advance program and presentation schedule can be found here.

Hotel

Hyatt Town Lake Hotel
208 Barton Springs Road
Austin, Texas 78704
Reservation Number: 1 (800) 233-1234 or (512) 477-1234

MTV2007 rate: Cut-off date is Nov 13.
Attendees must call 1-800 233 1234 or 1-512-477-1234 and make their reservations.
Mention IEEE Computer Society to get the negotiated rate of $169 per night

Conference Registration

Register online by clicking here.
On/Before 3pm EST, 30 November 2007 After 3pm EST, 30 November 2007
IEEE Member $400                                                IEEE Member $500
Non-Member $495                                                  Non-Member $620
Student Member $300                                            Student Member $375
Student Non-Member $375                                    Student Non-Member $450
Life/Retired Member $300                                      Life/Retired Member $375
Tutorial $100                                                             Tutorial $100
Tutorials are canceled at this point; please don't register for them

Description - Workshop Scope

The purpose of MTV'07 is to bring together researchers and practitioners from all areas of work related to verification and test in order to exchange innovative ideas and present new methodologies for solving the challenges facing us today in various processor and SOC design environments. The workshop will take place in Austin, Texas, the live music capital of the world.

Areas of Interest

Validation of microprocessors and SOCs
Experiences on test and verification of high performance processors and SOCs
Test/verification of multimedia processors and SOCs
Performance testing
High-level test generation for functional verification
Emulation techniques
Silicon debugging
Formal techniques and their applications
Verification coverage
Test generation at the transistor level
Equivalence checking of custom circuits
Circuit level verification
Switch-level circuit modeling
Timing verification techniques
Path analysis for verification or test
Design error models
Design error diagnosis
Design for testability or verifiability
Optimizing SAT procedures for application to testing and formal verification

Organizing Committee

Finance:	Jennifer Dworak (Brown Univ)
Publication:	Alper Sen (Freescale)
Panel:	Al Crouch (Inovys)
Publicity:	Tao Feng (Cadence)
Committee:	Moshe Levinger (IBM - Israel)
European/Canadian	Andreas Veneris (U. of Toronto)

Program Committee

Jacob Abraham (UT-Austin); Miron Abramovici (DAFCA); Hussain Al-Asaad (UC-Davis); Tony Ambler (UT-Austin); Eyal Bin (IBM - Haifa); Shawn Blanton (CMU); Melvin Breuer (USC); Ken Butler (TI); K.-T. (Tim) Cheng (UCSB); Nick Dutt (UCI); Sujit Dey (UCSD); Ajit Dingankar (Intel); Franco Fummi (Universita `di Verona); Mike Garcia (Freescale); Sandeep Gupta (USC); Ian Harris (U. Mass.); John Hayes (U. Michigan); Eric Hennenhofer (Obsidian, Inc.); Jim Holt (Freescale); Alan J.Hu (UBC, Canada); T.M.Mak (Intel); Anmol Mathur (Calypto); Hillel Miller (Freescale); Sankaran Menon (Intel); Ishwar Parukar (Sun); Carl Pixley (Synopsys, Inc.); Paolo Prinetto (Poli di Torino)
WangQi Qiu, Pextra Corp: Nur Touba (UT-Austin); Miroslav Velev; Vivekananda Vedula (Intel); Cheng-Wen Wu (National Tsing-Hua University); Paul R Zehr (Intel); Yervant Zorian (VirageLogic)

Past MTV workshop Information

MTV 2006: MTV 2006 page