University of California, Santa Barbara
Department of Electrical and Computer Engineering

Synthesis and CAD
ECE 156B, Winter 2004
Instructor: Prof. Li-C. Wang
licwang@ece.ucsb.edu
(805)893-5916 
Schedule: Class: TTH 3:30-4:45 pm at 387-103
Office: Room 3161, Engineering I
Office Hour: 2-3pm T,Th

Syllabus
can be found HERE

TAs Office Hours and Discussion/Lab Session

Leonard Lee
Office Hours: Mon 3-4pm, Wed 2-3pm, Fri 9-11am
E-mail: lylee@ece.ucsb.edu
Location: Engineering I, 2164
Discussion/Lab Session: Announcement of dates in class, via e-mail, and here

Online Class Orgazination

Date Lecture Topic Homework Solutions Notes
January 6, 2004 Administration Lecture Syllabus - - -
January 8, 2004 Lecture 1 Overview of Design Methodologies - - -
January 13, 2004 Lecture 2 Design Compiler & Synthesis of Language Constructs - - Updated Set-up information for Design Compiler can be found here. Set-up of Cygwin for your home computer or for any Windows machine can be found here
January 15, 2004 Lecture 2 Synthesis of Language Constructs HW #0 (Design Compiler Tutorial) due 1/22/04 - -
January 20, 2004 Lecture 3 Timing (Introduction) - - -
January 22, 2004 Lecture 3 & Lecture 4 Timing (Introduction & Physical Causes/Statistical) - - -
January 27, 2004 Lecture 4 & Lecture 5 Timing (Physical Causes/Statistical & Clock) HW #1 Counter design/synthesis (class.v) - -
January 29, 2004 Lecture 5 & Lecture 6 Timing (Clock & Power) - - -
February 3, 2004 No Class - - - Instructor attending TAU Workshop.
February 5, 2004 TAU Workshop (PS Version) & Lecture 7 Summary of TAU Workshop (PS Version included due to PDF font error) & Boolean Decision Diagrams HW #1 Due
HW #2 Sequential Machine Synthesis		 - -
February 10, 2004 Lecture 7 Boolean Decision Diagrams - - -
February 12, 2004 Lecture 8 (PDF Version) Boolean Satisfiability HW #2 Due - -
February 17, 2004 In Class Test - - - Worth 20% of your grade (Lectures 1-8)
February 19, 2004 Test #1 Solutions Handed back tests and went over solutions HW #3 BDD & SAT - Leonard will give lecture, Instructor went to Euro-DATE 2004
February 24, 2004 Lecture 9 Introduction to Logic Synthesis - - -
February 26, 2004 Lecture 10 Synthesis of 2-level Logic - Exact Method HW #3 Due
HW #4 A Simple Processor		 - -
March 2, 2004 Lecture 11 Synthesis of 2-level Logic - Heuristic Method - - -
March 4, 2004 Lecture 12 Synthesis of Multi-level Logic - - -
March 9, 2004 Review Slides Review HW #4 Due - -
March 11, 2004 No class Leonard will be in the classroom to answer questions about the final - - -
March 19, 2004 Final Exam 4-7 PM, same room - - - Worth 30% of your grade

Projects And Homework

You will be using Design Compiler (DC), the synposys synthesis tool. For DC, you can only use it in the ECI lab. Hence, please get an account in the ECI lab if you don't have one now. Also, you are expected to know ModelSim (also available in the ECI lab) or a similar Verilog simulator from ECE 156A.

Electrical and Computer Engineering || College of Engineering