Basic test knowledge: Ask yourself, do you understand the following concepts?

• Fault models like stuck-at, bridging, transition faults, path delay faults
• ATPG search
• Defective part level and DPL prediction models (Williams-Brown Model)
• Scan test and functional test
• Test compression
• SAT and SAT based ATPG

Delay test: Ask yourself, are you familiar with delay testing concepts? You may need to read Chapters 1-6 of this good book on delay testing.

• Two-vector pattern test
• Transition fault ATPG
• Critical path and speed path
• Path delay ATPG, sensitization criteria of a path
• SAT-based path delay ATPG
• Speed binning, functional mode vs. scan mode
• Correlation of functional delay testing to scan delay testing

Timing analysis: Ask yourself, do you feel comfortable about the following?

• Static timing analysis algorithm
• Building a timing model
• Statistical STA algorithms (Canonical-form representation)
• Statistical timing models
• Models of process variations, spatial correlation models
• Design timing closure
• Critical path selection and ranking

Programming skills: Are you familiar with various programming skills? (Are you familiar with standard programming interface such as STL C++ library, or a parser builder like Bison?)

• Basic data structures: Stack, Queue, Hashing, Binary tree, Array of pointers, Graph, etc.
• You probably want to get familiar with STL C++ library on using basic data structures and algorithms
• Basic algorithms: Sorting, Search algorithms, Branch and Bound, Local search, Genetic algorithm
• Parsers: Do you know how to write a parser to parse a circuit netlist, a timing model, a design data format like XML? Do you know how to use a parser builder like Bison?
• ATPG: Do know know how to write an ATPG?
• SAT: Can you take a SAT solver and write a SAT-based path delay fault ATPG?
• Simulators: Can you write a fault simulator? Can you write a timing simulator based on a given fixed-delay timing model?
   

For 1173.001, the project started on Jan 1, 2004. You can find the progressive reports here (username: src, password: src1578). Where this research is going can be found at this NSF project proposal with references.

Our focus of research is to solve problems after design timing closure and before mass production. If you are not familiar with what problems to solve, you probably want to review my TTEP tutorial slides. We can divide the problems into several categories:

• Pre-silicon simulation and analysis: The simulation and analysis tools are more accurate with the objective to support test preparation and silicon debug. An example of this can be the Pattern-based statistical timing analysis tool.

• Timed ATPG and statistical timed ATPG: The objective is to build an ATPG tool that can extend the ATPG analysis to include timing information or even statistical timing information. An example can be the Learning-driven statistical timing ATPG approach.

• Timing diagnosis and debug: The objective is to extend the traditional research in diagnosis and debug to consider process variations. For example, statistical diagnosis is quite different from traditional diagnosis as stated in this paper. I think to go further, the statistical diagnosis has to be combined with Design-for-Manufacturing (DFM) techniques such as Identifying and Matching Problematic Layout Patterns.

• Test preparation and test optimization: The objective is to develop the best test sets or the optimal test strategy in delay test or speed binning. To begin the thinking of this direction, we have been work on Test Pattern Selection. This is only a very small step to achieve Test Optimization. In general, we need to think, after analyzing the test results from the 1st silicon samples, what can we do to improve our test pattern set or to improve our test strategy?

• Test data mining and learning: To support diagnosis, debug, and test optimization, test data mining and learning techniques should be invented. However, so far we have not yet proposed something concrete enough to be called Test Data Mining. This will continuously be the question driving us.

In summary, to be able to pursue research in this area, you need to get yourself familiar with the skills and knowledge listed on the left-hand side. You need to understand the materials covered in the TTEP tutorial. Also, you need to understand the basic algorithms in data mining and learning. Then, we can start the discussion of how to apply various learning techniques to solve problems in this domain.

Working on the existing tools:

A good way to get yourself familiar with the concepts and skills listed on the left-hand side is to work on something that is real. So far we have developed various tools and methodologies. You can pick up the code of a tool and try to extend it or develop some simplified versions of the codes.

• Statistical timing model: You need to get familiar with this model and also, try to develop and enhance the model so that it can be incorporated with our tools.

• Pattern-based statistical timing analyzer: This tool takes a pattern and simulate it based on the statistical timing model. The simulation is hazard-aware as described in the paper. You can extend it to consider other timing effects such as spatial correlations, cross-talks, MISs, etc.

• Statistical static timing analyzer: This tool implements the IBM SSTA methodology. The enhancement is to allow spatial correlations to be learned from the silicon path delay testing results as described in this DAC submission. You can take this tool and add various features to it, such as selection of critical paths and add a SAT-based path delay ATPG to it.

After you read the book, you can try to develop some simple codes to do:

• Transition fault and path delay fault simulation (logic analysis only)

• ATPG for path delay fault

• Critical path classification (logic analysis only)

• Path classification and path simulation by considering timing

Developing those simple tools can help you understand the concepts as well as help you to practice your coding ability.