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2004 - 2005 list

(2003 and before list can be found here)

  1. “A comparison of BDDs, BMC, and sequential SAT for model checking” Parthasarathy, G.; Iyer, M.K.; Cheng, K.-T.; Wang, L.C.; High-Level Design Validation and Test Workshop, 2003. Eighth IEEE International 12-14 Nov. 2003 Page(s):157 – 162

  2. “Critical path selection for delay fault testing based upon a statistical timing model” Wang, L.-C.; Jing-Jia Liou; Kwang-Ting Cheng; Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Volume 23,  Issue 11,  Nov. 2004 Page(s):1550 – 1565

  3. “Safety property verification using sequential SAT and bounded model checking” Parthasarathy, G.; Iyer, M.K.; Cheng, K.-T.; Wang, L.-C.; Design & Test of Computers, IEEE Volume 21,  Issue 2,  Mar-Apr 2004 Page(s):132 – 143

  4. “Multilevel circuit clustering for delay minimization” Sze, C.N.; Ting-Chi Wang; Wang, L.-C.; Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Volume 23,  Issue 7,  July 2004 Page(s):1073 – 1085

  5. “A new sigma-delta modulator architecture for testing using digital stimulus” Chee-Kian Ong; Kwang-Ting Cheng; Wang, L.-C.;Circuits and Systems I: Regular Papers, IEEE Transactions on,Volume 51,  Issue 1,  Jan. 2004 Page(s): 206 – 213

  6. “New challenges in delay testing of nanometer, multigigahertz designs” Mak, T.M.; Krstic, A.; Cheng, K.-T.; Wang, Li.-C.; Design & Test of Computers, IEEE Volume 21,  Issue 3,  May-June 2004 Page(s):241 - 248

  7. “A signal correlation guided circuit SAT solver” Feng Lu, Li-C. Wang, Kwang-Ting Cheng, John Moondanos, Ziyad Hanna Journal of Universal Computer Science, Vol 10, Issue 12, 2004, pages 1629-1654

  8. “Efficient reachability checking using sequential SAT” Parthasarathy, G.; Iyer, M.K.; Cheng, K.T.; Wang, L.C.; Design Automation Conference, 2004. Proceedings of the ASP-DAC 2004. Asia and South Pacific 27-30 Jan. 2004 Page(s):418 – 423

  9. “Jitter spectral extraction for multi-gigahertz signal” Ong, C.-K.; Hong, D.; Cheng, K.-T.; Wang, L.-C.; Design Automation Conference, 2004. Proceedings of the ASP-DAC 2004. Asia and South Pacific 27-30 Jan. 2004 Page(s):298 – 303

  10. “Improved symbolic simulation by functional-space decomposition”  Tao Feng; Wang, L.-C.; Kwang-Ting Cheng; Design Automation Conference, 2004. Proceedings of the ASP-DAC 2004. Asia and South Pacific 27-30 Jan. 2004 Page(s):634 – 639

  11. “TranGen: a SAT-based ATPG for path-oriented transition faults” Kai Yang, Kwang-Ting Cheng, Li-C. Wang Design Automation Conference, 2004. Proceedings of the ASP-DAC 2004. Asia and South Pacific 27-30 Jan. 2004 Page(s): 92 - 97  

  12. “Regression simulation: applying path-based learning in delay test and post-silicon validation” Wang, L.-C.; Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings Volume 1,  16-20 Feb. 2004 Page(s):692 - 693 Vol.1

  13. “Improved symoblic simulation by dynamic funtional space partitioning” Tao Feng; Wang, L.-C.; Kwang-Ting Cheng; Lin, A.C.-C.; Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings Volume 1,  16-20 Feb. 2004 Page(s):42 - 47 Vol.1

  14. “Pattern selection for testing of deep sub-micron timing defects” Mango; Chao, C.-T.; Wang, L.-C.; Kwang-Ting Cheng; Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings Volume 2,  16-20 Feb. 2004 Page(s):1060 - 1065 Vol.2

  15. “Random Jitter Extraction Technique in a Multi-Gigahertz Signal” Ong, C.-K.; Hong, D.; Cheng, K.-T.; Wang, L.-C.; Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings Volume 2,  16-20 Feb. 2004 Page(s): 10286

  16.  “A scalable on-chip jitter extraction technique” Chee-Kian Ong; Dongwoo Hong; Kwang-Ting Cheng; Wang, L.-C.; VLSI Test Symposium, 2004. Proceedings. 22nd IEEE 25-29 April 2004 Page(s):267 – 272

  17. “On path-based learning and its applications in delay test and diagnosis” Li-C. Wang, T.M. Mak, Kwang-Ting Cheng, Magdy S. Abadir, Proceedings of the 41st ACM/IEEE annual conference on Design automation, June 2004, Pages: 492 - 497  

  18. “An efficient finite-domain constraint solver for circuits” Parthasarathy, G.; Iyer, M.K.; Cheng, K.T.; Wang, L.C.; Proceedings of the 41st ACM/IEEE annual conference on Design automation June 2004 Pages: 212 - 217  

  19. “Static Statistical Timing Analysis for Latch-based Pipeline Design” Mango C-T Chao, Li-C. Wang, Kwang-Ting Cheng, Sandip Kundu IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2004, pages 468 – 472

  20. “A Path-Based Methodology for Post-Silicon Timing Validation” Leonard Lee, Li-C. Wang, T. M. Mak, Kwang-Ting Cheng, IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2004, pages 713-720

  21. “On correlating structural tests with functional tests for speed binning of high performance design” Zeng, J.; Abadir, M.; Vandling, G.; Wang, L-C..; Kolhatkar, A.; Abraham, J.; IEEE International Test Conference, 2004. Proceedings  26-28 Oct. 2004 Page(s):31 - 37

  22. “An Efficient Sequential SAT Solver With Improved Search Strategies” Lu, F.; Iyer, M.K.; Parthasarathy, G.; Wang, L.-C.; Cheng, K.-T.; Chen, K.C.; Design, Automation and Test in Europe, 2005. Proceedings 07-11 March 2005 Page(s):1102 – 1107

  23. “On Silicon-Based Speed Path Identification” Leonard Lee, Li-C. Wang, Praveen Parvathala, T M Mak VLSI Test Symposium, 20044 Proceedings. 23nd IEEE 1-4 May 2005 Page(s): 35-41

  24. “On A Software-Based Self-Test Methodology and Its Application” Charles H-P Wen, Li-C. Wang, Kwang-Ting Cheng, Kai Yang , Wei-Ting Liu , Ji-Jan Chen, VLSI Test Symposium, 20044 Proceedings. 23nd IEEE 1-4 May 2005 Page(s): 107-113

  25. “Reducing Pattern Delay Variations for Screening Frequency-Dependent Defects” Benjamin N. Lee, Li-C. Wang, Magdy S. Abadir  VLSI Test Symposium, 20044 Proceedings. 23nd IEEE., 1-4 May 2005 Page(s): 153-159

Last updated: 05/02/2005
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