Submitted:
Sean Hsi, Benjamin N Lee, Li-C Wang and Magdy Abadir
Cost-Sensitive Statistical Learning for Test Optimization.
Submitted to Desigh Automation Conference, 2007.
Applying Random Forests to delay test.
Pouria Bastani, Benjamin N Lee, Li-C Wang and Magdy Abadir
Mining test data for ranking cells in terms of timing uncertainties.
Submitted to Design Automation Conference, 2007.
Data mining post-silicon test results to determine which cells are most
uncertain.
Benjamin N Lee, Li-C Wang and Magdy Abadir
Issues on Test Optimization with Known Good Dies and Known Defective Dies - A Statistical Perspective .
Accepted to International Test Conference (
ITC), 2006. (also presented at
ITSW, 2006)
Initial work on training SVMs for delay test.
Benjamin N Lee, Li-C Wang and Magdy Abadir
Refined Statistical Static Timing Analysis Through
Learning Spatial Delay Correlations.
Accepted to Design Automation Conference (
DAC), 2006. (also presented at
TAU, 2006)
In this work, we proposed a Bayesian inference framework for learning important
parameters from a manufactured chip.
Benjamin N Lee, Hui Li, Li-C Wang and Magdy Abadir
Hazard-aware Statistical Timing Simulation and Its Applications in Screening Frequency-dependent Defects
Proc. International Test Conference (
ITC), November 2005
We extend a statistical pattern simulator to handle hazards and allow for uncertainty-based test-pattern selection.
Benjamin N Lee, Li-C Wang and Magdy S. Abadir
Reducing Pattern Delay Variations for Screening Frequency-dependent Defects
Proc. IEEE VLSI Test Symposium (
VTS), May 2005
Statistical timing analysis has been proposed from mainly a static, pattern-less perspective. In this paper, we look at it from a pattern-based perspective and examine how it can be used for testing, in particular for reducing the pattern delay variation of a test pattern set.
Jason Kwok-san Lee, Benjamin N Lee, Jeremy Thorpe, Kenneth Andrews, Sam Dolinar, Jon Hamkins
A Scalable Architecture of a Structured LDPC Decoder
IEEE Symposium on Information Theory, 2004
LDPC error-correcting codes offer excellent performance for reasonable complexity. In this work, we discuss a scalable FPGA hardware implementation of an LDPC decoder.
The Lutonium: A Sub-Nanojoule Asynchronous 8051 Microcontroller
Proc. 9th IEEE International Symposium on Asynchronous Systems & Circuits (ASYNC), May 2003
This work describes the design of an ultra low-power, fully asynchronous version of the popular 8051 microcontroller.