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TTEP2006: A tutorial proposal was submitted for ITC 2006. You can download the outline of tutorial here. The current tutorial slides can be downloaded here. So far, we have divided the reference list into the following categories:
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(still under construction ...) Last update:
12/11/2005 07:58:45 AM Modeling of variations
This seems like a very good tutorial. I
found it on the web site. This is probably the 1st paper to read
before reading other papers. Some understanding of the
manufacturing process is required. This is a paper widely referenced by
others working in statistical timing. This is a journal version
of their paper in ICCAD 2000 shown below. I think what this
paper talks about has something to do with the Fmax prediction
paper by S G Duvall shown in the section of "Fmax prediction"
below. You may want to read both papers carefully. They are
quite interesting. This seems to be one of the latest
papers from this group on the topic. It should have the most
up-to-date references and information.
This is another widely referenced
paper.
This is a tutorial paper. It clearly
described how statistical approaches should be used in circuit
modeling and optimization. It mentions the use of the Response
Surface Model techniques. This paper is from Intel and I think
the work (and the person) is quite influential in Intel. Analysis and decomposition of spatial variation in integrated circuit processes and devices Stine, B.E.; Boning, D.S.; Chung, J.E.; Semiconductor Manufacturing, IEEE Transactions on ,Volume: 10 , Issue: 1 , Feb. 1997 Pages:24 - 41 This paper compares the relative
importance of device and interconnect variability. Corrections
are made based on parameters affecting locally vs. those
affecting globally. This paper is a good introductory paper
for statistical process control, an area with long history. In the area of parameter extraction
from process, the concept of statistical inference has been used
a lot. This is similar to silicon learning at the high level,
where design parameters are learned from chip behavior. This is
a good paper to describe the parameter extraction at process
level.
Another good paper to learn about
process parameter characterization.
Modeling and forecasting
of manufacturing variations
Nassif, S.R.;Statistical
Metrology, 2000 5th International Workshop on , 11 June 2000,
Pages:2 - 10Modeling
and forecasting of manufacturing variations
Nassif, S.R.; Design
Automation Conference, 2001. Proceedings of the ASP-DAC 2001.
Asia and South Pacific , 30 Jan.-2 Feb. 2001 Pages:145 - 149 The impact of variability on power Nassif, S.R.;Low Power Electronics and Design, 2004. ISLPED '04. Proceedings of the 2004 International Symposium on , 9-11 Aug. 2004 Pages:350 Delay variability: sources, impacts and trends Nassif, S.;Solid-State Circuits Conference, 2000. Digest of Technical Papers. ISSCC. 2000 IEEE International , 7-9 Feb. 2000 Pages:368 - 369 Modeling the effects of manufacturing variation on high-speed microprocessor interconnect performance Mehrotra, V.; Nassif, S.; Boning, D.; Chung, J.;Electron Devices Meeting, 1998. IEDM '98 Technical Digest., International , 6-9 Dec. 1998 Pages:767 - 770 Spice up your MOSFET modelling Yu Cao; Orshansky, M.; Sato, T.; Sylvester, D.; Chenming Hu;Circuits and Devices Magazine, IEEE ,Volume: 19 , Issue: 4 , July 2003 Pages:17 - 23
Efficient generation of
pre-silicon MOS model parameters for early circuit design New paradigm of predictive MOSFET and interconnect modeling for early circuit simulation Cao, Y.; Sato, T.; Orshansky, M.; Sylvester, D.; Hu, C.;Custom Integrated Circuits Conference, 2000. CICC. Proceedings of the IEEE 2000 , 21-24 May 2000 Pages:201 - 204 Intra-field gate CD variability and its impact on circuit performance Orshansky, M.; Milor, L.; Ly Nguyen; Hill, G.; Yeng Peng; Chenming Hu;Electron Devices Meeting, 1999. IEDM Technical Digest. International , 5-8 Dec. 1999 Pages:479 - 482 Statistical circuit characterization for deep-submicron CMOS designs Chen, J.; Orshansky, M.; Chenming Hu; Wan, C.-P.;Solid-State Circuits Conference, 1998. Digest of Technical Papers. 45th ISSCC 1998 IEEE International , 5-7 Feb. 1998 Pages:90 - 91
Combining model development with
characterization
Scharfetter, D.; Duvall, S.;
Circuit sensitivity to
interconnect variation
Lin, Z.; Spanos, C.J.; Milor,
L.S.; Lin, Y.T.; Statistical modeling for analog designs - mismatch
Statistical modeling of device
mismatch for analog MOS integrated circuits
An asymptotically constant,
linearly bounded methodology for the statistical simulation of
analog circuits including component mismatch effects
SiSMA: a statistical simulator for
mismatch analysis of MOS ICs
Biagetti, G.; Orcioni, S.;
Signoracci, L.; Turchetti, C.; Crippa, P.; Alessandrini, M.;Computer
Aided Design, 2002. ICCAD 2002. IEEE/ACM International
Conference on , 10-14 Nov. 2002 Pages:490 - 496 Parameter extraction via test chips (a few papers as examples) Interesting paper talks about PCA and
RSM methods in statistical analysis.
Evaluation of transistor property
variations within chips on 300-mm wafers using a new MOSFET
array test structure
Izumi, N.; Ozaki, H.; Nakagawa,
Y.; Kasai, N.; Arikado, T.; Semiconductor Manufacturing,
IEEE Transactions on , Volume: 17 , Issue: 3 , Aug. 2004
Pages:248 - 254
Characterisation of the threshold
voltage variation: a test chip and the results Test-circuit-based extraction of inter- and intra-chip MOSFET-performance variations for analog-design reliability Matsumoto, S.; Mattausch, H.J.; Ooshiro, S.; Tatsumi, Y.; Miura-Mattausch, M.; Kumashiro, S.; Yamaguchi, T.; Yamashita, K.; Nakayama, N.; Custom Integrated Circuits, 2001, IEEE Conference on. , 6-9 May 2001 Pages:357 - 360
An electrical test structure to
evaluate linewidth variations due to proximity effects in
optical lithography
Fallon, M.; Stevenson, J.T.M.;
Walton, A.; Gundlach, A.M.; A simple test structure for accurately monitoring channel doping variations in a MOSFET Joardar, K.;Microelectronic Test Structures, 1994. ICMTS 1994. Proceedings of the 1994 International Conference on , 22-25 March 1994 Pages:77 - 80 This is the only paper I found with MIS
statistical timing model. The 2nd author at Intel works on the
MIS problem without statistical variations (for industrial use).
The 1st author did the intern at Intel 2003-04. This work was
done at Intel. This paper is referenced a lot by the
paper just above. The MIS modeling above is an extension from
the MIS modeling in this paper, which is not statistical.
Variable reduction in MOS timing models Zukowski, C.; Chen, D.-P.;Computer Design: VLSI in Computers and Processors, 1988. ICCD '88., Proceedings of the 1988 IEEE International Conference on , 3-5 Oct. 1988 Pages:124 - 128
PARADE: parametric delay
evaluation under process variation [IC modeling]
Statistical modeling of gate-delay
variation with consideration of intra-gate variability
Okada, K.;
Yamaoka, K.; Onodera, H.;Circuits and Systems, 2003. ISCAS
'03. Proceedings of the 2003 International Symposium on
, Volume: 5 , 25-28 May 2003 Pages:V-513 - V-516 vol.5
Design for variability in DSM
technologies [deep submicron technologies] Process related issues (a few papers as examples) (key paper) Subwavelength lithography and its potential impact on design and EDA Kahng, A.B.; Pati, Y.C.;Design Automation Conference, 1999. Proceedings. 36th , 21-25 June 1999 Pages:799 - 804
Experimental study of threshold
voltage fluctuation due to statistical variation of channel
dopant number in MOSFET's
Mizuno, T.; Okumtura, J.;
Toriumi, A.;Electron Devices, IEEE Transactions on , Volume:
41 , Issue: 11 , Nov. 1994 Pages:2216 - 2221 Is gate line edge roughness a first-order issue in affecting the performance of deep sub-micro bulk MOSFET devices? Shiying Xiong; Bokor, J.; Qi Xiang; Fisher, P.; Dudley, I.; Paula Rao; Haihong Wang; En, B.;Semiconductor Manufacturing, IEEE Transactions on , Volume: 17 , Issue: 3 , Aug. 2004 Pages:357 - 361 Intrinsic parameter fluctuations in decananometer MOSFETs introduced by gate line edge roughness Asenov, A.; Kaya, S.; Brown, A.R.; Electron Devices, IEEE Transactions on , Volume: 50 , Issue: 5 , May 2003 Pages:1254 - 1260 This paper explains why DFM was not
used popularly.
Physical CAD changes to
incorporate design for lithography and manufacturability
Toward a methodology for
manufacturability-driven design rule exploration Design for manufacturability in submicron domain Maly, W.; Heineken, H.; Khare, J.; Nag, P.K.;Computer-Aided Design, 1996. ICCAD-96. Digest of Technical Papers., 1996 IEEE/ACM International Conference on , 10-14 Nov. 1996 Pages:690 - 697 Design rule methodology to improve the manufacturability of the copper CMP process Lakshminarayanan, S.; Wright, P.; Pallinti, J.;Interconnect Technology Conference, 2002. Proceedings of the IEEE 2002 International , 3-5 June 2002 Pages:99 - 101
Design for manufacturability: a
key to semiconductor manufacturing excellence Statistical parameter control for optimum design and manufacturability of VLSI circuits Bolt, M.J.B.; Engel, J.; v.d. Klauw, C.L.M.; Rocchi, M.;Semiconductor Manufacturing Science Symposium, 1990. ISMSS 1990., IEEE/SEMI International , 21-23 May 1990 Pages:99 - 106
Analysis of the impact of
proximity correction algorithms on circuit performance (Best paper)
Electrical characterization of the
copper CMP process and derivation of metal layout rules
Lakshminarayanan, S.; Wright,
P.J.; Pallinti, J.
Page(s): 668- 676 Statistical timing analysis and Fmax prediction (key paper) Statistical timing analysis based on a timing yield model Najm, F.N.; Menezes, N.;Design Automation Conference, 2004. Proceedings. 41st , June 7-11, 2004 Pages:460 - 465 (key paper) First-order incremental block-based statistical timing analysis Visweswariah, C.; Ravindran, K.; Kalafala, K.; Walker, S.G.; Narayan, S.; Design Automation Conference, 2004. Proceedings. 41st , June 7-11, 2004 Pages:331 - 336 (key paper) Statistical timing analysis considering spatial correlations using a single PERT-like traversal Hongliang Chang; Sapatnekar, S.S.;Computer Aided Design, 2003. ICCAD-2003. International Conference on , 9-13 Nov. 2003 Pages:621 - 625 (key paper) Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration Bowman, K.A.; Duvall, S.G.; Meindl, J.D.;Solid-State Circuits, IEEE Journal of ,Volume: 37 , Issue: 2 , Feb. 2002 Pages:183 - 190 STAC: statistical timing analysis with correlation Jiayong Le; Xin Li; Pileggi, L.T.; Design Automation Conference, 2004. Proceedings. 41st , June 7-11, 2004 Pages:343 - 348 Fast statistical timing analysis handling arbitrary delay correlations Orshansky, M.; Bandyopadhyay, A.;Design Automation Conference, 2004. Proceedings. 41st , June 7-11, 2004 Pages:337 - 342
Statistical timing analysis for
intra-die process variations with spatial correlations Block-based static timing analysis with uncertainty Devgan, A.; Kashyap, C.; Computer Aided Design, 2003. ICCAD-2003. International Conference on , 9-13 Nov. 2003 Pages:607 - 614 Maximum clock frequency distribution model with practical VLSI design considerations Bowman, K.A.; Samaan, S.B.; Hakim, N.Z.;Integrated Circuit Design and Technology, 2004. ICICDT '04. International Conference on , 2004 Pages:183 - 191
Statistical timing for parametric
yield prediction of digital integrated circuits
A methodology to
improve timing yield in the presence of process variations
Static timing analysis based
circuit-limited-yield estimation Timing yield estimation from static timing analysis Gattiker, A.; Nassif, S.; Dinakar, R.; Long, C.;Quality Electronic Design, 2001 International Symposium on , 26-28 March 2001 Pages:437 - 442 A Methodology for Worst-Case Analysis of Integrated Circuits Nassif, S.R.; Strojwas, A.J.; Director, S.W.;Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on ,Volume: 5 , Issue: 1 , January 1986 Pages:104 - 113
A general probabilistic framework
for worst case timing analysis
Orshansky, M.; Keutzer, K.;
Design Automation Conference, 2002. Proceedings. 39th , 10-14
June 2002 Pages:556 - 561 1. Statistical diagnosis without prior knowledge about the potential holes --- post-silicon learning *. On post-silicon speed path identification, submitted paper to VTS 2005 a. On path-based learning and its applications in delay test and diagnosis, DAC 2004 b. A path-based methodology for post-silicon timing validation, ICCAD 2004 2. Statistical diagnosis with prior knowledge about the potential holes --- solving the "matching problem" The problem of statistical diagnosis was defined in the DATE 2003 paper. However, in that paper, the diagnosis is defined based on a defect model. Hence, the term "statistical diagnosis" then referred to "statistical diagnosis with prior knowledge about the potential problems." In DATE 2003 work, the assumption is that there could be only a few defects (or problems) randomly located across the circuit. This assumption breaks down if the problem is due to design holes where the effect can be "distributed" across the entire circuit. Hence, in a later work in ITC 2003, we study the possibility of using the framework presented in DATE 2003 to diagnose problems whose effects are distributed across the entire circuit. The DAC 2004 work was actually inspired by the limitations in ITC 2003 work. As you might find out, if the problems are distributed (1 problem affects the timing of many parts of the circuit, like a design modeling error), the effectiveness of the DATE 2003 diagnosis framework can be limited. Hence, we started to develop a new diagnosis methodology without assuming a fault/error model. a. Delay Defect Diagnosis Based Upon Statistical Timing Models -- The First Step, DATE 2003. b. Diagnosis-Based Post-Silicon Timing Validation Using Statistical Tools and Methodologies, ITC 2003 3. Critical path selection --- no need to test many paths
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