Software tools developed through the project Task ID 1173.001 - Statistical Timing Simulation Tools and Methodologies for Speed Test and Performance Validation funded by Semiconductor Research Corporation (SRC) include:

• Statistical timing model based on a 90nm technology file

• Monte Carlo statistical static timing analyzer

• Monte Carlo statistical pattern-based timing analyzer

• Block-based statistical static timer

• Pattern-based statistical timing simulator

• Statistical timed and timed ATPG

Updates can be founded in this page dedicated to SRC project.