FPGA Based AES Encryption Processor

ECE 253 Embedded Systems Design

Brett Brotherton

Nick Callegari

Project Proposal

            With computer security becoming a large concern with more personal information sent across the internet, encryption of data is very important to protect the confidentiality of that data.  However, encryption is computationally intensive and can take up a large amount of execution time especially in embedded systems, which often have much less processing power than a normal PC.  A good solution is to have hardware based encryption, which greatly speeds up the process and frees up lots of processor time.  FPGAs are a natural choice for developing hardware encryption cores because of the ease of reconfigurability.  Not only does it lower design time and cost, it also allows for future updates to newer and better encryption standards without having to replace the system. 

            We propose to develop an FPGA based AES encryption core.  AES is a popular encryption standard and has been adopted by the US government.  This core will be designed to receive data from an off-chip source, and encrypt the data using the AES encryption standard and to send the data back off chip.  The heart of this design is a Xilinx Virtex-4 field programmable gate array (FPGA).  The Virtex-4 pro FPGA allows us to custom configure a MicroBlaze softcore processor to serve as the basis for our design.  The Xilinx EDK development environment allows us to develop applications for the Microblaze and to add custom peripherals and to tune various features on the processor such as cache and memory size.  We will use the EDK to add an AES Encryption core that will interface with the Microblaze processor.  There will also be an interface to off chip SDRAM and a serial interface to allow communication between the system and a PC. 

            The system will be controlled by the PC through the serial interface.  Ideally we will be able to send data and a key and a command to encrypt/decrypt to the chip through the serial interface.  The chip will perform the operation and send back the encrypted/decrypted data. 

            This platform will serve as a testing/demonstration for current and future RCSec research projects.  Our main goal is to develop a solid platform that can be used to demonstrate our various security techniques.  Once we have completed the basic functioning system we can try to incorporate more features into it.  First, we would like to partition the design using “motes,” and then analyze it with our route tracing tool.  This however may not be possible since Jbits does nots currently support Virtex-4 FPGAs.   We would also like to analyze and compare any difference in performance this technique has on the design.  Second, we would like to try and incorporate Ted Huffmire's memory reference monitor into the design to demonstrate its effectiveness and analyze its affect on performance. 

            We believe that given the problem at hand this will prove as a possible solution for fast and efficient decryption/encryption of data.  Not only does it prove as a great project for the 10 weeks given for the project, it also is very scalable for future research and development in to real life concepts. 

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