Leonard Yang Lee
lylee (at) ece.ucsb.edu
ECE Department
University of California
Santa Barbara
		Leonard and Jacqueline

Education history:
PhD. Jan. 2007		MS. Dec. 2005		BS. Jun. 2002
Electrical & Computer Engineering		Electrical & Computer Engineering		Computer Science & Engineering
University of California		University of California		University of California
Santa Barbara		Santa Barbara		Los Angeles

Research interests:

• Applying theory developed in statistics, mathematics, and other fields into CAD applications.
• Thesis: applying theory developed in statistics to analyze design sensitivity to process variations, with cross-coupling as a driver example.

Publications:

• L.-C. Wang, A. Krstic, L. Lee, K.-T. Cheng, and M. Abadir. Using Logic Models to Predict the Detection Behavior of Statistical Timing Defects. in Proc. IEEE International Test Conference, pp. 1041-1050, Sep. 30-Oct. 2, 2003.
• L. Lee, L.-C. Wang, T. M. Mak, and K.-T. Cheng. A Path-Based Methodology for Post-Silicon Timing Validation. in Proc. International Conference on Computer-Aided Design, pp. 713-720, Nov. 7-11, 2004.
• L. Lee, L.-C. Wang, P. Parvathala, T. M. Mak. On Silicon-Based Speed Path Identification. in Proc. of IEEE VLSI Test Symp., pp. 35-41, May 1-5 2005.
• L. Lee, S. Wu, C. H.-P. Wen, L.-C. Wang. On Generating Tests to Cover Diverse Worst-Case Timing Corners. in IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 415-423, Oct. 3-5, 2005.
• L. Lee, L.-C. Wang. An Efficient Pruning Method to Guide the Search of Precision Tests in Statistical Timing Space. in Proc. IEEE International Test Conference, Paper 2.2, Oct. 24-26, 2006.
• L. Lee, L.-C. Wang. On Bounding the Delay of a Critical Path. in Proc. IEEE International Conference on Computer-Aided Design, pp. 81-88, Nov. 5-9, 2006.
• L. Lee, L.-C. Wang. Necessary and Sufficient Conditions for Bounding Design Sensitivity to Process Variations. submitted to Proc. IEEE Design Automation Conference, Jun. 2007.

Links:

• My Fianceé's Website