Biography

    Ph.D., Department of ECE, University of Texas at Austin, 1996
    MSCS, Department of Computer Sciences, University of Texas at Austin, 1991

Research Interests

    Statistical methods for test and diagnosis
    Microprocessor Test and Verification
    Data mining and learning algorithms for test and verification applications
    Design and test optimization

Prior Academic & Industry Experiences

   Assistant Professor, Computer Engineering Group,
       Department of ECE, University of California -
       Santa Barbara, California, Spring 2001- Spring 2004.
   Assistant Professor, Computer Engineering Group,
       Department of EE, Texas A&M University,
       College Station, Texas, Spring 1999 - Fall 2000.
    CAD Research Consultant, Test and Verification, PowerPC Design Team,
       Motorola, Austin, Texas, 1/1/1999 - 12/31/2000.
    CAD Research & Development, Test & Verification - Tools and Methodologies,
       Somerset PowerPC Design Center, Motorola, Austin, Texas, March 1996- Dec 1998.
    Member of Technical Staff, Mathematics Research Center,
       AT&T Bell Labs, Murray Hill, NJ, 1991-1995 summers

Honors & Awards

    Best Panel Award, IEEE VLSI Test Symposium (VTS), 2003
   Best Paper Award, Design Automation and Test Conference in Europe, 2003
   Best Paper Award, IEEE VLSI Test Symposium (VTS), 1999
   Best Paper Award,  Design Automation and Test Conference in Europe, 1998
    Motorola Silver Quill Award
    SRC Graduate Fellowship, 1993-1996

Professional Services

   Program Chair and co-founder,
      IEEE Microprocessor Test and Verification Workshop (MTV)
   Steering Committee,
       IEEE Test SynthesisWorkshop (ITSW) and IEEE Test Economic Workshop
    Program Committee, IEEE VLSI Test Symposium 03-05,
       IEEE High-level Test and Validation Workshop (HLDVT),
       International  Conference on Computer Design (ICCD), 
       Asian Test Symposium (ATS04, 05)
    Track Chair, Test and Verification Track,
       IEEE International Symposium on Quality of Electronic Design (ISQED04, 05, 06)
   Guest Editor, IEEE Design and Test of Computer (D&T),
       Special issue on speed binning and special  issue on functional verification

Courses:

• ECE 156A, Fall 05
• ECE 156B, Winter 04
• ECE 255B, Spring 04

Here is my publication up to 2003

Additional publication can be found at this publication page