===================================================================== Call For Participation: IEEE 5th International Workshop on Microprocessor Test & Verification (MTV 2004) Hyatt Town Lake Hotel, Austin, Texas, USA September 9-10, 2004 Web Site: http://mtv.ece.ucsb.edu/mtv04.html old MTV website: http://dropzone.tamu.edu/MTV/ --------------------------------------------------------------------- Deadlines: - Advance Workshop Reservation: August 16, 2004, 5pm USA EST (***Extended to August 23, 5pm USA EST) - Advance Hotel Registration: August 18, 2004 (***Extended to August 22) $118 single and $143 double MTV'04 Workshop Registration and Hotel Reservation are available at http://mtv.ece.ucsb.edu/mtv04.html Hyatt Town Lake Hotel, 208 Barton Springs Road, Austin, Texas 78704 Reservation Number: 1 (800) 233-1234 or (512) 477-1234 http://austin.hyatt.com/property/index.jhtml The MTV04 Program includes an excellent Keynote Address, 8 Technical Sessions, and 1 panel. Technical sessions at a glance: *Functional Test Generation *SOC Test *Modeling and Verification Method *SAT and Applications *Functional Verification *Advanced Test Issues *Micro Architecture Verification (Industrial Presentations) *Test and Debug (Industrial Presentations) *Panel - Why did high-level verification not move forward as fast as we want in the industry? --------------------------------------------------------------------- Preliminary Program Wednesday, September 8 6-9pm: Reception & On-Site Registration ===================================================================== Thursday, September 9 7:30-8:30am: Continental Breakfast ------------------------------------------------------------- 8:30-9:30am: Keynote Speech: Mark McDermott Vice President of Engineering, AMCC embedded products group ------------------------------------------------------------- Session A Chair: Magdy Abadir, Motorola 9:30-10:45 Functional Test Generation A.1 "TiGeR, the Transmeta Instruction GEneratoR: A production based, pseudo random instruction, x86 test generator" Anshuman S Nadkarni, Tom Kenville, Transmeta Corporation, Santa Clara, CA A.2 "Techniques in Post Silicon Functional Test Generation" Paul R. Zehr, Intel Corporation, Santa Clara, CA A.3 "Automatic Test Programs Generation Driven by Internal Performance Counters" W. Lindsay, E. Sanchez, M. Sonza Reorda, G. Squillero, Dip. Automatica e Informatica, Politecnico di Torino, Italy ------------------------------------------------------------- 10:45-11am: Coffee Break ----------------------------------------------------------- Session B Chair: Al Crouch, Inovys 11-12:40pm: SOC Test B.1 "Compressing Functional Tests for Microprocessors" Kedarnath J. Balakrishnan, Nur A. Touba, and Srinivas Patil, University of Texas, Austin, and Intel Corp. B.2 "Compact ATPG for Concurrent SOC testing" Arkan Abdulrahman and Spyros Tragoudas, Southern Illinois University, IL B.3 "Practical Test IO Conscious Test Scheduling for SOCs" Chih-Yen Lo, Kuo-Liang Cheng, Chih-Ysun Huang, and Cheng-Wen Wu National Tsing Hua University, Taiwan B.4 "Using Infrastructure IPs to support SW-based Self-Test of Processors" P. Bernardi, M. Rebaudengo, M. Sonza Reorda, Dip. Automatica e Informatica, Politecnico di Torino, Italy ---------------------------------------------------------------- 12:40-2pm: Lunch ------------------------------------------------------------- Session C Chair: Jennifer Dworak, Brown University 2-3:40pm: Modeling and Verification Method C.1 "Extreme Formal Modeling (XFM) for Hardware Models" Syed Suhaib, Deepak Mathaikutty, David Berner, and Sandeep Shukla, Virginia Polytechnic and State University, VA C.2 "On Microprocessor and SOC Validation: A Simulation-Centric or Isomorphism-Centric Process?" Al Brown and Xinghao Chen, Boolean Dynamics Corp, NY, and City College of NY, New York C.3 "Formal Specification of an Asynchronous Processor via Action Redinement" Xiuli Sun and Jinzhao Wu, Chinese Academy of Science, Chengdu, China, and Universitat Mannheim, Germany C.4 "Embracing System Level Design" Rami Rachamim, Summit Design -------------------------------------------------------------- 3:40-4pm: Coffee Break ------------------------------------------------------------ Session D Chiar: Prabhat Mishra, University of Florida 4-5:15pm: SAT and Applications D.1 "Debugging Sequential Circuits Using Boolean Satisfiability" Moayad Fahim Ali, Andreas Veneris, Sean Safarpour, Magdy Abadir, Rolf Drechsler, and Alexander Smith, University of Toronto, Freescale Semiconductor, and University of Bremen, Germany D.2 "On the Impact of Structural Circuit Partitioning on SAT-based Combinational Verification" Marc Herbstritt, Thomas Kmieciak, Bernd Becker, Albert-Ludwigs-University, Germany D.3 "PICHAFF - A Hierarchical Parallel SAT Solver" Tobias Schubert, Bernd Becker, Albert-Ludwigs-University, Germany ------------------------------------------------------------- 6:30-9:30pm: Dinner and Social Event =================================================================== Friday, May 30 7:30-8:30am: Continental Breakfast ------------------------------------------------------------- Session E Chair: Eyal Bin, IBM 8:45-10am: Functional Verification E.1 "Robust Vera Coding Techniques for Gate-Level and Tester-Compliant SoC Verification Environments" Mark Litterich, and Joachim Geishauser, Verilab Ltd, and Motorola, Inc. E.2 "Functional Verification of Pipelined Processors: A Case Study" Prabhat Mishra and Nikil Dutt, and Yaron Kashai UC-Irvine, and Verisity Design Inc. CA E.3 "A Verification Methodology for Reconfigurable Systems" M. Borgatti, A Fedeli, U. Rossi, ST-Microelectronics J-L. Lambert I. Moussa, TNI-Valiosys F. Fummi, G. Pravadelli, C. Marconcini, Universita di Vernona ------------------------------------------------------------- 10-10:15am: Coffee Break ------------------------------------------------------------- Session F Chair: Ian Harris, UC-Irvine 10:15-11:55pm: Advance Test I F.1 "A Circuit Level Fault Model for Resistive Shorts of MOS Gate Oxide" Xiang Lu, Zhou Li, Wangqi Qiu, D.M.H. Walker, and Weiping Shi, Department of EE, Department of CS, Texas A&M University, College Station F.2 "Correlating Structural Tests and Functional Tests for Speed Binning" J. Zeng, M. Abadir, G. Vandling, L. Wang, A. Karako, J. Abraham, Freescale Semi, Cadence Design Inc, UC-Santa Barbara, UT-Austin F.3 "Diagnosis of Failed Segments for Path Delay Faults" Min-Pin Kuo and Jing-Jia Liou, National Tsing-Hua University, Taiwan F.4 "Reducing Structural Bias: An Initial Look at Observation Diversity" Jennifer Dworak, James Wingfield, and M. Ray Mercer, Department of EE, Texas A&M University --------------------------------------------------------------- 11:55-1pm: Lunch ------------------------------------------------------------ Session G Chair: T. M. Mak, Intel 1pm-2:15pm: Micro-Architecture Verification Special session for invited speech G.1 Neeta Ganguly, Intel Corp. G.2 Ben Sander, AMD G.3 Eyal Bin, IBM ------------------------------------------------------------ 2:15-2:30pm: Coffee Break ------------------------------------------------------------- Session H Chair: Andreas Veneris, Univ. of Toronto 2:30-3:45pm: Test and Debug Issues Special session for invited speech H.1 "How do we test for adaptive computing?" T. M. Mak, Intel H.2 "Debug Feature that Structural Testers Need to Support" Al Crouch, Inovys Corp. H.3 Memory Testing is not just about Algorithms, nor just about Memories" Al Crouch, and Nikhil Dakwala, Inovys Corp. and Stridge Inc. ------------------------------------------------------------- 3:45-4pm: Coffee Break ------------------------------------------------------------- Session I Chair: Narayanan Krishnamurthy, Freescale Semiconductor 4pm-5:30pm: Panel Panel - Why did high-level verification not move forward as fast as we want in the industry? 4-5 panelists from EDA vendors will present their views ------------------------------------------------------------- 5:30pm: Close --------------------------------------------------------------------- Registration All workshop participants are required to register. Registration forms are available online at https://mtv.ece.ucsb.edu/mtv04.html Important Dates: 16 August 2004 Advance registration ends 5:00 pm Eastern Time, late fees apply 16 August 2004 Cancellation deadline -- cancellations MUST be in writing 16 August 2004 All wire transfers and check payments must be received to avoid on-site registration and payment. 23 May 2003 Late registration ends After this date you must register and pay onsite. Early Registration* IEEE/CS Member $395 IEEE Student Member $250 Non-Member $495 Student Non-Member $325 IEEE Life Member $250 On-Site Registration IEEE/CS Member $495 IEEE Student Member $325 Non-Member $595 Student Non-Member $405 IEEE Life Member $325 Advance Hotel Registration: August 18, 2004 Hyatt Town Lake Hotel, 208 Barton Springs Road, Austin, Texas 78704 Reservation Number: 1 (800) 233-1234 or (512)477-1234 http://austin.hyatt.com/property/index.jhtml Please use "IEEE Computer Society MTV" Single $118, Double $143 Proceedings Informal proceeding will be made available to all attendees. This will include extended abstracts, summaries, or papers provided by authors based on their presentations. Information For further information, please contact Li-C. Wang, Tel: 805-893-5916 E-mail: licwang@ece.ucsb.edu ---------------------------------------------------------------------