Microprocessor Test and Verification (7-9 December 2009)

List of Accepted Papers/Panels/Tutorials

• "Day 3" Tutorials & DVClub event on Dec 9 (free with MTV registration)

  • 8am-11am: Tutorial #1 by Neil Songcuan. Using Rapid Prototyping for Microprocessor Design Verification
  • 12noon-1:30pm: DVClub.org Austin Chapter lunch and technical lecture by Sakar Jain and Robert Page. Verification of the QorIQ Communication Platform’s CoreNet Fabric with SystemVerilog
  • 2:30pm-5:30pm: Tutorial #2 by Nikhil Dakwala. Why DFT, Design and Verification Teams must collaborate for efficient Silicon Debug

• Panel

  • Bhanu Kapoor, Shireesh Verma, John Goodenough, Ryan Pinto and Shankar Hemmady. Role of Simulation-Based Verification in Power Managed Designs

• Technical Presentation Sessions (Dec 7 & Dec 8 )

  1. Verification issues for multi-core systems
     • Jim Holt. System-level Performance Verification of Heterogeneous Multicore Systems-on-Chip
     • Peter Sewell. Towards rigorously defined architectures for relaxed-memory multiprocessors
     • Ganesh Gopalakrishnan. Dynamic Verification Methods for Message Passing
     • Bernd Becker, Matthew Lewis and Tobias Schubert. DPLL-based Reasoning in a Multi-Core Environment
  2. Architecture Verification
     • Zdenek Prikryl, Karel Masarik, Tomas Hruska and Adam Husar. Fast Cycle Accurate Interpreted Simulation
     • Jack Mason. The importance of full target environment simulation tests for architecture validation: A case study
     • Vyas Venkataraman, Di Wang, Wei Qin, Mrinal Bose and Jayanta Bhadra. Simulation of a heterogeneous system at multiple levels of abstraction using Rendezvous based modeling
     • Luis Angel Bathen, Yongjin Ahn, Sudeep Pasricha and Nikil Dutt. A Methodology for Power-aware Pipelining via High-Level Performance Model Evaluations
  3. Mutation Analysis
     • Alper Sen. Coverage Metrics for SystemC using Mutation Analysis
     • Nicola Bombieri, Franco Fummi and Graziano Pravadelli. On the Mutation Analysis of SystemC TLM-2.0 Standard
  4. Advanced Verification Techniques
     • Jingzhe Xu, Hyungbae Park and Jusung Park. Design of Efficient On-Chip Debugger for SoC
     • Subodh Sharma, Todd Dukes, Jayanta Bhadra and Ganesh Gopalakrishnan. Symbolic Execution Engine to Explore Path Feasibility in Assembly Programs
     • James Lear. Digital and Mixed-Signal Verification Differences
     • Sumit Ahuja and Sandeep Shukla. Verification Methodologies to Facilitate Aggressive Power Reduction
  5. Formal Verification
     • Mona Safar, Watheq El-Kharashi, Mohamed Shalan and Ashraf Salem. A Reconfigurable Five Stages Pipelined SAT Solver
     • Xiushan Feng, Brian Mcminn, Richard Bartolotti and Mark Eslinger. Using Backward Symbolic Justification to Constrain Initial State Don't-Cares in Model Checking
     • Daniel Grosse, Hoang M. Le and Rolf Drechsler. Induction-based Formal Verification of SystemC TLM Designs
  6. Verification of Microprocessors and Complex IPs
     • Giovanni Perbellini, Franco Fummi, Davide Quaglia, Saul Saggin and Sara Vinco. Mixing Simulated and Actual Hardware Devices to Validate Device Drivers in a Complex Embedded Platform
     • Padmaraj Singh, David Landis and Vijay Narayanan. Test Generation for Precise Interrupts on Out-of-Order Microprocessors
     • Robert Page and Sakar Jain. Verification of the QorIQ Communication Platform Containing CoreNet Fabric with SystemVerilog
     • Kai-Yuan Jan, Charles H.-P. Wen and Youn-Long Lin. A Learning-based Test-selection Strategy for Video Encoders
  7. Manufacturing Test
     • József Sziray. Switch-Level Test Calculation for CMOS Circuits
     • Shadi Moazzeni and Amin Emami. An Optimized Simulation-based Fault Injection and Test Vector Generation Using VHDL to Calculate Fault Coverage
     • Chia-Ying (Janine) Chen, Jing Zeng and Li-C Wang. Correlating System Test Fmax with Structural Test Fmax and Process Monitoring Measurements
  8. Verification Management
     • Allan Cochrane and Alan Hunter. Automating Verification Management
     • Richard Bartolotti, Tom Burd, Brian McMinn and Arun Chandra. Constraint Management and Checking in Template-Based Circuit Designs